Erulappan Sakthivel, Muruganantham Arunraja, Veluchamy Malathi
3. Distributed Energy Efficient Clustering Algorithm for WSN - Informacije MIDEM
4. VELAN: Variable Energy Aware Sense Amplifier Link for Asynchronous NoC
- Circuis and Systems
5. Distributed Similarity based Clustering and Compressed Forwarding for WSN - ISA transactions
10. FSM Based DFS Link for Network on Chip - Circuits and Systems
E Sakthivel, V Malathi, M Arunraja Microprocessors and Microsystems 38 (7), 692-706 2 2014
Now-a-days there is much research attempts aim to find out low power consumption in the area of Network-on-chip (NoC), both in architectural as well as algorithmic approach. Even though a lot of Double Tail Sense Amplifiers (DTSA) are used in architectural approach, the conventional DTSA with transceiver exhibits a difficulty of consuming more energy than its indented design during heavy traffic condition. Multiple sense amplifiers with transceiver for high performance improvement in NoC Architecture (MATHA) is designed in this research to eliminate the difficulty. This MATHA is a combination of recon- figurable DTSA and transceiver. The reconfigurable DTSA consist of modified DTSA (M-DTSA), modified clock gating with DTSA (MCG-DTSA), Modified Dual Edge Triggered with DTSA (MDET-DTSA), Soft-DTSA (S-DTSA), graph theory based traffic estimator and multiplexer. Depending upon the traffic rate, one of the DTSA among the available four DTSA is selected and information transferred to the receiver. The proposed MATHA design is evaluated on TSMC 90 nm technology, showing 6.1 GB/s data rate and 0.32 W total link power.
E Sakthivel, V Malathi, M Arunraja Journal of Circuits, Systems and Computers 24 (09), 1550141 1 2015
In recent days, network-on-chip (NoC) researchers focus mainly on the area reduction and low power consumption both in architectural and algorithmic approach. To achieve low power and high performance in NoC architecture, sense amplifiers (SAs) introduced which can consume less power under various traffic conditions. In order to analyze the performance of architectural NoC design before fabrication level, the new simulator is developed based on multi core processor with improved sense amplifier (MCPSA) in this work. The MCPSA simulator provides user, the flexibility of incorporating various traffic configurations and routing algorithm with user reconfigurable option. In addition, the different SA model can be put into the simulation in plug and play manner for evaluation. The NoC case studies are presented to demonstrate the NoC architecture with double tail sense amplifier (DTSA) and modified-DTSA (M-DTSA) design. The performance metric such as delay, data rate and power consumption is evaluated. The main idea of this new simulator is to interface multisim environment (MSE) into a NoC environment for validating any DTSA.
M Arunraja, V Malathi, E Sakthivel Informacije MIDEM 45 (3), 180-187 1 2015
Wireless sensor networks (WSN) are powered by finite energy source like batteries, which imposes stringent energy boundaries. Clustering of nodes avoids redundant message transmissions over the network. Thus conserves energy, communication bandwidth and achieves scalability. Here we propose a Distributed Energy Efficient Clustering Algorithm (DECA), a deterministic clustering approach where Cluster Heads (CHs) are selected based on their residual energy and priority using passive clustering technique. Nodes then associate with the CH with least communication cost and high residual energy. This method achieves longer life span than the previous energy efficient clustering algorithms in both homogeneous and heterogeneous networks. DECA has extended the WSN life span to 30% in the homogeneous environment and 50% in the multi-level heterogeneous environment.
E Sakthivel, V Malathi, M Arunraja Circuis and Systems 7 (03), 128 2016
A real time multiprocessor chip paradigm is also called a Network-on-Chip (NoC) which offers a promising architecture for future systems-on-chips. Even though a lot of Double Tail Sense Amplifiers (DTSA) are used in architectural approach, the conventional DTSA with transceiver exhibits a difficulty of consuming more energy and latency than its intended design during heavy traffic condition. Variable Energy aware sense amplifier Link for Asynchronous NoC (VELAN) is designed in this research to eliminate the difficulty, which is the combination of Variable DTSA circuitry (V-DTSA) and Transceiver. The V-DTSA circuitry has following components such as bootable DTSA (B-DTSA) and bootable clock gating DTSA (BCG-DTSA), Graph theory based Traffic Estimator (GTE) and controller. Depending upon the traffic rate, the controller activates necessary DTSA modules and transfers information to the receiver. The proposed VELAN design is evaluated on TSMC 90 nm technology, showing 6.157 Gb/s data rate, 0.27 w total link power and 354 ps latency for single stage operation.
M Arunraja, V Malathi, E Sakthivel ISA transactions 59, 180-192 2015
Wireless sensor networks are engaged in various data gathering applications. The major bottleneck in wireless data gathering systems is the finite energy of sensor nodes. By conserving the on board energy, the life span of wireless sensor network can be well extended. Data communication being the dominant energy consuming activity of wireless sensor network, data reduction can serve better in conserving the nodal energy. Spatial and temporal correlation among the sensor data is exploited to reduce the data communications. Data similar cluster formation is an effective way to exploit spatial correlation among the neighboring sensors. By sending only a subset of data and estimate the rest using this subset is the contemporary way of exploiting temporal correlation. In Distributed Similarity based Clustering and Compressed Forwarding for wireless sensor networks, we construct data similar iso-clusters with minimal communication overhead. The intra-cluster communication is reduced using adaptive-normalized least mean squares based dual prediction framework. The cluster head reduces the inter-cluster data payload using a lossless compressive forwarding technique. The proposed work achieves significant data reduction in both the intra-cluster and the inter-cluster communications, with the optimal data accuracy of collected data.
M Arunraja, V Malathi, E Sakthivel Microprocessors and Microsystems 39 (6), 348-357 2015
Lifetime is one of the major Quality of Service factors for Wireless Sensor Networks (WSN). As sensor nodes are generally battery-powered devices, the network lifetime can be extended over a reasonable time span by lessening the energy consumption of nodes. Reducing the amount of data transmission can effectively minimize the energy consumption, the bandwidth requirement and network congestions. In a WSN, denser deployment of nodes results in a high spatial correlation between data generated by neighboring nodes. Slow varying nature of many physical phenomenon results in similar sensor observations over the period. In this proposed work, a two level data reduction technique is employed. Here the Data and Energy Aware Passive (DEAP) clustering approach is introduced to divide the sensor network into data similar clusters. A Dual Prediction (DP) based reporting is deployed between cluster members and their Cluster Head (CH). This first level data reduction is attributed to the temporal correlation of data over the time. In CHs, the data from multiple data similar nodes are aggregated to reduce the spatial data redundancy. The proposed method DEAP-DP is verified with real world datum and has achieved up to 68% data reduction at 0.5 C error tolerance.
M Arunraja, V Malathi KSII Transactions on Internet and Information Systems 9 (7), 2488-2511 2015
Data redundancy has high impact on Wireless Sensor Network’s (WSN) performance and reliability. Spatial and temporal similarity is an inherent property of sensory data. By reducing this spatio-temporal data redundancy, substantial amount of nodal energy and bandwidth can be conserved. Most of the data gathering approaches use either temporal correlation or spatial correlation to minimize data redundancy. In Collective Prediction exploiting Spatio Temporal correlation (CoPeST), we exploit both the spatial and temporal correlation between sensory data. In the proposed work, the spatial redundancy of sensor data is reduced by similarity based sub clustering, where closely correlated sensor nodes are represented by a single representative node. The temporal redundancy is reduced by model based prediction approach, where only a subset of sensor data is transmitted and the rest is predicted. The proposed work reduces substantial amount of energy expensive communication, while maintaining the data within user define error threshold. Being a distributed approach, the proposed work is highly scalable. The work achieves up to 65% data reduction in a periodical data gathering system with an error tolerance of 0.6°C on collected data.
M Arunraja, V Malathi, E Sakthivel IJISR - ISSR Journals
Bilateral filters use a wide range of medical and industrial applications. The limitations of conventional bilateral filter architecture are having a minimum kernel size and constant delay. This constant delay depends on two modules available in architecture such as the width of the image and sum of processing elements. Due to the inputs variation the kernel size can extent which may affect overall performance in terms of all the image quality assessment and performance in FPGA level (scalability, latency, power consumption). To evade this problem Low power, high speed FPGA based Novel Approach for Bilateral filter (NABI) are introduced. This NABI consists of Structure Shared Architecture (SSA), Master Control Unit (combination of intensity calculator and graph theory based traffic estimator), kernel based clock unit and Reconfigurable server. These components are described on the register transfer level implemented in VHDL. Depends upon the size of the kernel the reconfiguration is taking place via reconfigurable server. The intensity calculator is used to estimate the intensity of image and that intensity value is placed in normalization block to achieve better PSNR and MSE. This proposed NABI is implemented in a Virtex-5VLX50-1 device. The performance results in terms of FPGA level 31.69% slice reduction, 49.51% frame rate improvement, 28.96% power reduction and 50% latency reduction are achieved. The image quality assessment is also observed and compared with conventional algorithms. Thus, NABI work achieves better outcome than conventional work.
M Arunraja, V Malathi, E Sakthivel, G Perumalvignnesh Circuits and Systems, 2016, 7, 1760-1768
This paper describes the design and Field Programmable Gate Array (FPGA) based 4 × 4 breadth heuristic Multiple-Input—Multiple-Output (MIMO) decoder using 16 and 64 Quadrature Amplitude Modulation (QAM) schemes. The intention of this work is to observe the performance of Candidate Execution with Low Latency Approach for soft MIMO detector in FPGA (CELLA). The Smart Ordering and Candidate Adding (SOCA), Parallel Candidate Adding (PCA) and Backward Candidate Adding (BCA) give better performance in terms of Bit Error Rate (BER) or chip level service. In order to attain both BER and FPGA level performance in a single system, CELLA is developed in this work. Simulation and experimental results demonstrate the effectiveness of the proposed work under the system 4 × 4 MIMO-OFDM employing 16 QAM and 64 QAM. The proposed experiment is implemented in Xilinx Virtex 5 C5VSX240T. The performance results, in terms of FPGA level 76% slice reduction, 58.76% throughput improvement, 75% power reduction and 87% latency reduction, are achieved. The BER performance is observed and compared with the conventional algorithms. Thus, the proposed work achieves better outcome than the conventional work.
E Sakthivel, V Malathi, M Arunraja, G Perumalvignesh Circuits and Systems, 2016, 7, 1734-1750
As low power consumption is the main design issue involved in a network on chip (NoC), researchers are concentrating more on both algorithms and architectural approaches. The conventional Dynamic Frequency Scaling (DFS) and history based Frequency Scaling (HDFS) algorithms are utilized to process the energy constrained data traffic. However, these conventional algorithms achieve higher energy efficiencies, and they result in performance degradation due to the auxiliary latency between clock domains. In this paper, we present a variable power optimization interface for NoC using a Finite State Machine (FSM) approach to attain better performance improvement. The parameters are estimated using 45 nm TSMC CMOS technology. In comparison with DFS system, the evaluation results show that FSM-DFS link achieves 81.55% dynamic power savings on the links in the on-chip network, and 37.5% leakage power savings of the link. Also, this proposed work is evaluated for various performance parameters and compared with conventional work. The simulation results are superior to conventional work.
Dr.E.Sakthivel, Dr.V.Malathi, Dr.M.Arunraja Asian Journal of Research in Social Seience and Humanities.
An On-chip communication is a promising communication platform for enormous System on-Chip (SoC) designs. To ease the interconnection and bandwidth limitation problems in SoC design, a new communication platform is introduced i.e. Network on-Chip. A Conventional real time Sakthivel et al. (2016). Asian Journal of Research in Social Sciences and Humanities, Network on Chip (NoC) router requires more area for implementation and its clock distribution is deterministic, and also it suffers high power consumption and low speed execution. To overcome these limitations a new algorithm is proposed in this paper an Extended Application Algorithm (EAA) Link, this novel algorithm which is applicable for all real time bio-NoC (RTBNoC) to reduce the power consumption. The EAA link for real time bio-medical gives 23% of reduction in energy usage when compared with other conventional real time NoC. The Real-time Network onChip implemented in SPARTAN 3 FPGA and its power and thread activities monitored using a GUI. Experimental results show that EAA link successfully adjusts link frequency and voltage Depends upon the packet size and threads allocated to the modules, This EAA Link method is applicable for all real-time bio-medical applications, which afford a guaranteed service without any performance degradation in On-chip communication.
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